Controlled Impedance FR4 PCB – 50Ω / 90Ω / 100Ω

Controlled Impedance FR4 PCB – 50Ω / 90Ω / 100Ω
50Ω single-ended – GPS, cellular, Bluetooth, WiFi, RF antennas
90Ω differential – USB 2.0/3.0, LVDS, camera interfaces
100Ω differential – Ethernet (100BASE-T, 1000BASE-T), HDMI
Standard tolerance ±10% – ±8% or ±5% available on request
Precise trace width & spacing – calculated from your stackup
TDR testing available – time domain reflectometry verification
Impedance test coupons – included on panel or separate
4+ layers recommended – ground plane adjacent to signal layers
Free impedance stackup design – engineering support included

Product Details
FAQs

Controlled Impedance FR4 PCB – 50Ω / 90Ω / 100Ω

Modern high-speed digital and RF designs require precise impedance control to maintain signal integrity. Without controlled impedance, reflections occur, data becomes corrupted, EMI increases, and products fail certification.

Our Controlled Impedance FR4 PCB supports the three most common industry-standard impedances:

Impedance	Type	Common Applications
50Ω	Single-ended	GPS, Cellular (4G/5G), Bluetooth, WiFi, RF antennas
90Ω	Differential	USB 2.0, USB 3.0/3.1, LVDS (Low-Voltage Differential Signaling), Camera interfaces
100Ω	Differential	Ethernet (100BASE-T, 1000BASE-T), HDMI, DisplayPort, PROFINET

Why Controlled Impedance Matters

Problem Without Impedance Control	Consequence
Signal reflections	Data errors, corrupted communication
Overshoot / ringing	Potential damage to ICs
EMI / radiated emissions	FCC/CE certification failure
Reduced noise margin	Intermittent failures, field returns
Poor eye diagram opening	Limited cable length, unstable links

Controlled impedance ensures consistent characteristic impedance along each trace, matching driver and receiver, thereby minimizing reflections and maintaining signal integrity.

How Impedance is Controlled on FR4

Impedance on FR4 is determined by four key parameters:

Parameter	Impact on Impedance	Controlled By
Trace width (W)	Wider = lower impedance	PCB layout (Gerber)
Trace spacing (S)	Wider spacing (differential) = higher impedance	PCB layout (Gerber)
Dielectric thickness (H)	Thicker dielectric = higher impedance	PCB stackup (layer thickness)
Dielectric constant (Dk)	Higher Dk = lower impedance	FR4 material selection (Dk ~4.2-4.6)

How we achieve your target impedance:

You specify target impedance (50Ω, 90Ω, 100Ω) and tolerance
We recommend copper weight, layer thickness (prepreg/core), and stackup
We calculate trace width (and spacing for differential) for your specific stackup
We fabricate with process controls (etching, lamination) maintaining ±10% tolerance
Optional TDR testing – verify impedance on finished boards

Standard Impedance Specifications

Parameter	Standard Capability	Advanced Capability
50Ω single-ended	±10%	±8% or ±5%
90Ω differential	±10%	±8% or ±5%
100Ω differential	±10%	±8% or ±5%
Custom impedance	±10%	±8% or ±5%
Test method	TDR (Time Domain Reflectometry) or impedance coupons	Same
Documentation	Impedance test report included	Same

Note: Tighter tolerance (±5% or ±8%) may require additional process controls and testing – please inquire.

Impedance Test Structures (Coupons)

We include impedance test coupons on each production panel:

Coupon Type	Placement	Purpose
50Ω coupon	Panel edge or customer-defined location	Verify single-ended impedance
90Ω coupon	Panel edge or customer-defined location	Verify USB/LVDS differential impedance
100Ω coupon	Panel edge or customer-defined location	Verify Ethernet/HDMI differential impedance

For prototype orders with single pieces (no panel): We can include impedance coupons on an additional small board or use similar panel data.

Impedance test report included with each controlled impedance order.

Layer Stackup Recommendations

Board Complexity	Recommended Stackup	Impedance Layers
2-layer	Not recommended (no ground plane reference)	Avoid – inconsistent results
4-layer	Top (Signal) / Ground / Power / Bottom (Signal)	Top layer (L1) referenced to L2 ground
6-layer	Top / Ground / Signal / Power / Ground / Bottom	L1 to L2 ground, L3 to L4 power, L6 to L5 ground
8+ layers	Multiple signal + ground layers	Various reference planes

Minimum recommendation: 4-layer PCB with signal layer adjacent to ground plane for consistent impedance.

2-layer boards: Impedance control is possible but not recommended due to inconsistent reference (copper pour vs. no pour). We recommend 4+ layers for controlled impedance.

Technical Specifications for Controlled Impedance FR4 PCB

Parameter	Capability
Supported impedances	50Ω, 90Ω, 100Ω (custom available)
Tolerance standard	±10% (industry standard)
Tolerance advanced	±8% or ±5% (on request)
Test method	TDR (Time Domain Reflectometry)
Test coupons	Included on production panels
Layer count	4+ layers recommended (2-layer possible but not recommended)
Base material	FR4 (Standard or High TG)
Dielectric constant (Dk)	4.2-4.6 (frequency dependent)
Trace width/spacing (for impedance)	Calculated per stackup (typically 4-8 mil)
Surface finish	ENIG preferred (flat surface, consistent Dk)
Documentation	Impedance test report included

Applications Requiring Controlled Impedance

Application	Impedance	Why Required
GPS receiver	50Ω	Antenna matching – satellite signal integrity
Cellular module (4G/5G)	50Ω	RF performance, radiated power, sensitivity
Bluetooth / WiFi	50Ω	Antenna matching – range and throughput
USB 2.0	90Ω differential	Data integrity up to 480 Mbps
USB 3.0/3.1	90Ω differential	5-10 Gbps – extremely sensitive
LVDS (camera, display)	90Ω or 100Ω differential	Video data integrity
Ethernet (100BASE-T)	100Ω differential	Network reliability
Gigabit Ethernet (1000BASE-T)	100Ω differential	1 Gbps – requires tight control
HDMI / DisplayPort	100Ω differential	Video/audio integrity
Automotive radar (ADAS)	50Ω	Safety-critical signal integrity

Standard FR4 vs. Controlled Impedance

Feature	Standard FR4 PCB	Controlled Impedance FR4 PCB
Impedance tolerance	Uncontrolled (±20-30% or more)	Controlled (±10% standard)
Trace width design	Rule-of-thumb (e.g., 10 mil)	Calculated from stackup
Stackup design	Standard (e.g., 1.6mm total)	Customized for impedance
Test coupons	Not included	Included on panel
Impedance testing	None	TDR test + report
Documentation	COC only	Impedance test report included
Best for	Low-speed, non-critical signals	High-speed, RF, USB, Ethernet, HDMI
Cost	Baseline	+15-30% (coupons + testing + engineering)
Lead time	Standard	+1-3 days (test coupon design)

Impedance Tolerance Comparison

Tolerance	Difficulty	Cost Impact	Typical Applications
±15%	Easy	Minimal	Non-critical high-speed
±10%	Standard	Baseline (+15-30% vs. non-controlled)	USB 2.0, 100Mb Ethernet
±8%	Moderate	+5-10% vs. ±10%	USB 3.0, Gigabit Ethernet
±5%	Difficult	+15-25% vs. ±10%	High-speed (>5 Gbps), RF precision

Industry standard: ±10% – sufficient for most applications including USB 2.0, 100Mb Ethernet, Bluetooth/WiFi.

TDR (Time Domain Reflectometry) Testing

TDR is the industry-standard method for verifying impedance:

Aspect	Description
How it works	Sends fast rise-time pulse down the trace, measures reflected energy
What it measures	Characteristic impedance along entire trace length
Output	Impedance vs. distance graph + pass/fail determination
Defects detected	Opens, shorts, impedance discontinuities (connectors, vias, corners)

We provide TDR test reports showing measured impedance values with min/max/average.

High-Speed Design Recommendations

For best impedance control results:

Recommendation	Why
4+ layers minimum	Signal layer adjacent to ground plane
Use ground planes, not grids	Solid copper provides consistent reference
Avoid splitting reference plane under signals	Causes impedance discontinuities
Maintain consistent dielectric thickness	Use standard prepreg/core thicknesses
Avoid 90° corners	Use 45° or rounded corners
Keep differential pairs length-matched	Within 5-10 mils (0.13-0.25mm)
Maintain consistent trace spacing	No necking or widening
Minimize via count	Each via adds impedance discontinuity
Remove unused pads from inner layers	Reduces capacitive loading

Submit your design for free DFM review with impedance control recommendations.

Why Manufacture Your Controlled Impedance FR4 PCB With Us?

Feature	What You Get
Standard ±10% tolerance	Suitable for most high-speed applications
Tighter tolerance available	±8% or ±5% on request
TDR testing	Verification with test report included
Impedance coupons	Included on production panels
Custom stackup design	We calculate trace width/spacing for your target impedance
Free engineering support	DFM review with impedance recommendations
4+ layer capability	Up to 12+ layers (2-layer possible but not recommended)
100% electrical test	Plus impedance test coupons

Order Process for Controlled Impedance FR4 PCB

Upload Gerber files – specify target impedance(s), tolerance, and which layers
Free stackup design – we calculate trace width/spacing, recommend materials
Review and approve stackup + test coupon location
Fabrication – with process controls for impedance
TDR testing – verify impedance on coupons (or actual traces on request)
Impedance test report – included with shipment
Secure shipping

Q1: What is controlled impedance and why do I need it?

A: Controlled impedance means manufacturing PCB traces to a precise characteristic impedance (measured in Ohms), matching driver/receiver impedance to minimize reflections.

Why needed:

Low-speed (<10 MHz) – Not generally required; impedance variations don’t matter
High-speed (>10 MHz) / RF – Required – lack of control leads to signal reflections, data corruption, EMI, and certification failures

If your design includes USB, Ethernet, HDMI, LVDS, GPS, WiFi, Bluetooth, cellular, DDR memory, or high-speed ADCs – you need controlled impedance.

Q2: What is the standard tolerance for controlled impedance?

A: Industry standard: ±10% – sufficient for most applications including USB 2.0 (480 Mbps), 100 Mb Ethernet, Bluetooth, WiFi.

Tighter tolerances available:

±8% – USB 3.0 (5 Gbps), Gigabit Ethernet
±5% – High-speed (>5 Gbps), RF precision applications

Recommendation: Use ±10% unless your application specifically requires tighter. Tighter tolerances add cost and lead time.

Q3: What is the difference between 50Ω, 90Ω, and 100Ω? Which one do I need?

Impedance	Type	Standard For
50Ω	Single-ended	GPS, cellular (4G/5G), Bluetooth, WiFi, RF antennas (most common single-ended standard)
90Ω	Differential	USB 2.0/3.0, LVDS (cameras, displays)
100Ω	Differential	Ethernet (100BASE-T, 1000BASE-T), HDMI, DisplayPort, PROFINET

Check your IC datasheet or reference design – it will specify required impedance.

Q4: Can you do controlled impedance on a 2-layer board?

A: Possible but not recommended. 2-layer boards lack a dedicated ground plane adjacent to the signal layer – reference becomes inconsistent (copper pour on bottom layer). This leads to:

Wider impedance variation
More sensitive to copper pour shape
Less repeatable between boards

Our recommendation: Use 4-layer minimum for controlled impedance. The cost difference is small compared to reliability improvement.

Q5: What information do you need to calculate impedance?

A: To calculate trace width/spacing for your target impedance, we need:

Target impedance(s) – e.g., 50Ω, 90Ω differential
Tolerance – ±10% standard (specify if ±8% or ±5% needed)
Signal layers – which layers have impedance traces
Board thickness – e.g., 1.6mm (or we can recommend)
Layer count and stackup – if you have a preferred stackup (or we design for you)
Copper weight – e.g., 1 oz outer layers

If you don’t have stackup: Provide target impedance, layer count, and board thickness – we will design stackup and calculate trace width.

Q6: Do you provide impedance test reports?

A: Yes. Impedance test report included with every controlled impedance order.

Report includes:

Target impedance and tolerance
Measured impedance (min/max/average on coupons or actual traces)
TDR (Time Domain Reflectometry) waveform or pass/fail summary
Which coupon location(s) tested
Date and tester

For critical designs: We can test actual traces (not just coupons) – additional cost – please inquire.

Q7: How much does controlled impedance add to PCB cost?

A: Controlled impedance typically adds +15-30% vs. non-controlled FR4 PCB.

Cost factors:

Component	Cost Impact
Engineering (stackup design, trace calculation)	Minor (often absorbed for reasonable volumes)
Test coupon design and panel space	5-10% panel space used by coupons
TDR testing (test time, equipment)	5-15% depending on number of coupons
Tighter process controls (etching, lamination)	Small
Tolerance (tighter = more expensive)	±8%: +5-10%, ±5%: +15-25% vs. ±10%

Cost-benefit: For high-speed designs, cost of impedance control is small compared to field failure costs.

Q8: What is the minimum trace width for controlled impedance on FR4?

A: Typically 4-8 mil (0.10-0.20mm) – depends on stackup, dielectric thickness, and copper weight.

Dielectric Thickness (H)	1 oz Copper, 50Ω (approx.)
4 mil (0.10mm)	3.5-4.5 mil
6 mil (0.15mm)	5.5-6.5 mil
8 mil (0.20mm)	7.5-8.5 mil

If calculated trace width is too small (<4 mil): Increase dielectric thickness (add prepreg layers) or reduce copper weight.

We provide trace width recommendations during stackup design.

Q9: Can you do controlled impedance with ENIG surface finish?

A: Yes. ENIG works well for controlled impedance – flat surface consistent with impedance calculations. ENIG is preferred for controlled impedance + fine-pitch components.

Surface finish effects on impedance:

Finish	Effect	Recommendation
ENIG	Negligible (thin gold)	Recommended
HASL Lead-Free	Slight variation (uneven)	Acceptable but less ideal
OSP	Negligible	Acceptable
Immersion Silver	Negligible	Acceptable

Q10: What lead time should I expect for controlled impedance PCBs?

A: Controlled impedance adds ~1-3 days vs. standard PCB manufacturing.

Quantity	Standard FR4 PCB	Controlled Impedance (+ coupons + TDR)
Prototypes (1-20 pieces)	5-7 days	7-10 days
Mass production	8-12 days	10-14 days

Additional time factors:

Stackup design (if we are designing for you): +0-2 days
Tighter tolerance (±5% or ±8%): +2-3 days
Complex stackups with many impedance values: +1-2 days

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Controlled Impedance FR4 PCB – 50Ω / 90Ω / 100Ω